Traditionally, in the manufacture of integrated circuits, the contacts to polycrystalline silicon (poly-Si) and metal structures, and to diffusion regions, are designed such that a border region is provided surrounding the region where the contact is to be formed. Borders around the contacts are used primarily to ensure that under worst-case conditions, the contact openings will never extend beyond the structure or regions with which contact is to be made. If the border is not used, the contacts, due to normal process variations, may fall partially on the desired structure or regions and partially over adjacent structures or regions, thereby forming undesired connections.
While borders around contact windows ensure proper registration of the contacts and protection of the underlying conductive structures, they have the undesirable effect of limiting the maximum number of integrated circuits that can be packed in a given area. This limitation can be illustrated by the following example. If a standard bordered process has a one micron minimum dimension contact and a one micron minimum dimension poly-Si line, a one-half micron border must be placed around each contact. As a result, the poly-Si pad over which the contacts are placed must be approximately two microns in each dimension, or four square microns. In contrast a borderless process would not require any borders around the poly-Si contact, and a minimum dimension poly-Si line, in this case a one-half micron poly-Si line, could be used to make contact. As a result, the borderless technology would save approximately three square microns per contact structure. A borderless contact process allows an increased level of circuit integration, and hence an increased IC chip density.
Various techniques have been developed for forming borderless contacts, as disclosed in U.S. Pat. No. 4,944,682 (Cronin et al.), U.S. Pat. No. 4,966,870 (Barber et al.), and Research Disclosure #282, p A-144 (1987). The borderless contact processes described in these references involve depositing a conformal coating of material on a substrate so as to overlie pre-existing topography (e.g., poly-Si interconnect lines or an FET gate stack) and then depositing a second relatively void-free layer of material on top of the first layer. An opening for the borderless contact is formed in the second layer using an etchant that etches the second layer faster than the first layer, with the etch process generally being terminated when the opening extends entirely through the second layer to the first layer. Thus, the first layer serves as an etch stop for the etching process used to form the opening in the second layer. Then, a second etchant is used to extend the opening through the first layer to the selected underlying structure where contact is to be made.
For borderless contact processes of the type disclosed by Cronin et al. and Barber et al. to function effectively, the etching process used to form the opening in the second layer must be highly selective between the two layers. That is, the etching process used to etch the opening in the second layer should etch the second layer at a significantly faster rate than the first layer, with etch rate ratios (ERRs) in the range of at least 40:1 being preferred. Unfortunately, the etch selectivity of known etchants that may be used to etch the first and second layers is often not as great as needed. As a result, slight over etching of the second layer can result in the etching of an opening in the first layer (which typically is not intended to be etched). Thus, a need exists for a borderless contact process involving depositions and etching processes that together provide a higher etch selectivity than is typically available with known borderless contact processes.
The problem of selectivity becomes especially acute when submicron connections are to be created inside trenches of small dimension. Consider two closely spaced transistor gate electrodes (elements 3 and 4 in FIG. 1) which are to have contacts located between the gate electrodes. During processing, the (vertical) contact etch will be stopped by etch stop layer 9. A thick insulator layer 10A, 10B and 10C made of glass or similar material is laid over the whole area and the contact holes 17 and 19 are patterned and then etched through the glass to the etch stop layer 9. The dimensions of the contacts will thus be limited by the thickness of the etch stop layer 9 on the sidewall spacers 13 and 15. In particular, for FIG. 1, the etch stop layer 9 can be no thicker than the distance d from the lower edge of the insulator layer portion 10B to the structure 8 under the etch stop for contact to the diffusion 1. The thinner the etch stop, the more closely contacts can be packed. Unfortunately the chances of circuit failure due to breaking through the etch stop are thereby increased. The thicker the etch stop, the less chance of circuit failure due to breaking through the etch stop but the larger the dimensions associated with the contact.
There is thus a need for a process that can produce very small dimensions together with high protection of the bottom of the trench from breakthrough.
A second problem can be addressed when the etch stop layer is oxidizable. This will be seen in more detail below, but in broad terms, the problem arises either (1) when the etch stop layer is optimally deposited at a point in the fabrication process at which its physical/chemical properties as an etch stop and its functional/electrical properties in a circuit are incompatible, or (2) when, in a subsequent step, the etch stop layer will, itself, have to be etched in the presence of a material having a similar etch rate. In such instances oxidizable materials can be used as etch stops and after their function as etch stops is complete, they can be converted to more advantageous materials by oxidation. Poly-Si is particularly well suited for use as the etch stop layer 9 when the second layer is boron phosphorus silicate glass (BPSG) because the etch ratio between BPSG and poly-Si is good and the poly-Si can be subsequently oxidized to provide a good dielectric (SiO.sub.2) which can be etched with high selectivity relative to an underlying silicon layer.